(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of selective gate N-type and P-type electrodes using germanium implantation in the fabrication of integrated circuits.
(2) Description of the Prior Art
For 0.1 μm CMOS and below, poly gate depletion is one of the critical issues in achieving high performance devices. Polysilicon-germanium (PolySiGe) is an attractive gate material because of its lower gate depletion and boron penetration and better electron mobility. However, PolySiGe gates degrade NMOS performance while enhancing PMOS performance. The germanium dopant enhances depletion in PMOS and degrades poly depletion in NMOS. It is desired to form NMOS and PMOS gates selectively where N type gates are formed without SiGe and P type gates are formed with SiGe.
U.S. Pat. No. 5,918,116 to Chittipeddi and U.S. Pat. No. 6,063,670 B1 to Lin et al disclose dual gate oxide processes. U.S. Pat. No. 6,342,438 B2 to Yu et al teaches doping PMOS and NMOS regions differently before patterning polysilicon gates. U.S. Pat. No. 5,356,821 to Naruse et al discloses epitaxial growth of SiGe gates for both NMOS and PMOS. U.S. Pat. No. 6,376,323 B1 to Kim et al teaches PolySiGe gates for both PMOS and NMOS with selective doping. Co-pending U.S. patent application Ser. No. 10/266,425 filed on Oct. 8, 2002 discloses a method for forming SiGe gates having different Ge concentrations for PMOS and NMOS. Co-pending U.S. patent application Ser. No. 10/697,746 filed on Oct. 30,2003 discloses a method for forming SiGe gates for PMOS and polysilicon gates for NMOS using a dual deposition and patterning process.